1. Field of the Invention
The present invention relates to a semiconductor device for a liquid ejection head used for constituting a liquid ejection head for ejecting a liquid such as, for example, ink, and a liquid ejection head and a liquid ejection apparatus using such a semiconductor device for a liquid ejection head.
2. Related Background Art
A liquid ejection head for ejecting a liquid from an ejection orifice issued as a recording head of an ink jet system by using, for example, ink as a liquid and controlling an ejection of ink according to recording signals and adhering the ink on a recording medium. Further, the liquid ejection apparatus comprising such a liquid ejection head is, for example, applied as an ink jet recording apparatus.
Here, describing a recording method of the ink jet system, the ink jet recording method (liquid jetting recording method) is capable of a high speed recording to the extent that a generation of noises at an operating time is extremely small to be negligible, and moreover, it is extremely excellent to the extent that a recording can be made on a so-called plain paper without requiring special processing such as a fixing and the like, and therefore, recently it is becoming a mainstream of the printing system. In particular, in an ink jet recording head using thermal energy, heat energy generated by electrothermic exchanger (heater) is given to a liquid to selectively induce a bubbling phenomenon in the liquid, thereby allowing an ink liquid droplet to eject from the ejection orifice by its bubbling energy.
FIG. 13 shows a circuit structure of the recording head to be mounted on the ink jet system recording apparatus, which represents the conventional liquid ejection head. An electrothermic exchanging element (heater) and its drive circuit of this type of the recording head as disclosed, for example, in Japanese Patent Application Laid-Open No. H05-185594 can be formed on the same silicon semiconductor substrate by using a semiconductor processing technology.
As shown in FIG. 13, on the semiconductor substrate, there are provided a plurality of heaters (electrothermic exchanging elements) 101 for generating heat for ejecting an ink, and an n type power transistor 102 is connected to each heater 101 in order to supply a desired current to the heater 101. The one end of each heater 101 is commonly connected to a heater power source line VH, and the other end of each heater 101 is connected to a drain of the corresponding n type power transistor 102. The source of each n type power transistor 102 is connected to a ground line GNDH, respectively. Further, a shift register 116 is commonly provided for a plurality of these heaters 101 for supplying the current to each heater 101 and temporarily storing an image data to decide whether or not the ink is ejected from a nozzle (ejection orifice) of the recording head. The shift register 116 is provided with an input terminal to be inputted with a transfer clock signal CLK and an image data input terminal in which an image data DATA to turn ON and OFF the heater 101 is inputted in serial form. Each stage of the shift resister 116 corresponds to one each heater 101, respectively, and the output of each stage of the shift resister 116 is connected to a latch circuit 115 for recording and maintaining the image data for each heater 101 for every heater. Each latch circuit 115 inputs the output of the shift resistor 116, and at the same time, comprises a latch signal input terminal for inputting a latch signal LT for controlling latch timing. The latch signal LT is commonly inputted to each latch circuit 115. On the output side of each latch circuit 115, there is provided an AND circuit 114, respectively. The AND circuit 114 takes the output of the latch circuit 115 and a heat signal HE for deciding a timing to let the current flow to the heater 101 as an input. The heat signal HE is commonly inputted to each of the AND circuit 114, respectively. The output of the AND circuit 114 is inputted to the gate of the power transistor 102 connected to the corresponding heater 101 through a level conversion circuit 103. The level conversion circuit 103 is a circuit which converts the signal of a so-called theoretical level into a signal of amplitude of voltage capable of controlling the gate of the power transistor 102.
Here, the n type power transistor is a field-effect transistor, and for example, it is an nMOS transistor or a n type DMOS (Double Diffused MOS}.
Describing a circuit structure of the level conversion circuit 103, there are provided a first inverter circuit 208 for inverting the image data from the AND circuit 114 and a second inverter circuit 207 for further inverting a signal outputted from the first inverter circuit 208. The level conversion circuit 103 is supplied with a power from an inner power source line VHTM outputted from a voltage generating circuit 117. Further, in the level conversion circuit 103, the output of the second inverter circuit 207 is inputted to a first CMOS inverter circuit comprising a pMOS transistor 202 and an nMOS transistor 203. The source of the pMOS transistor 202 is connected to a first buffer pMOS transistor 201 for dividing a voltage supplied from the inner power source line VHTM to enable a first CMOS inverter circuit to be driven by a signal below 5V (a power source voltage of a logic unit is generally below 5V) which is an output voltage of the AND circuit 114. Similarly, there is provided a second CMOS inverter circuit, which comprises a pMOS transistor 205 and an nMOS transistor and is inputted with the output of the first inverter circuit 208, and the source of the pMOS transistor 205 is connected to a second buffer pMOS transistor 204. Here, the gate of the first buffer pMOS transistor 201 is connected to a connecting portion of a pair of transistors 205 and 206 which is the output portion of the second CMOS inverter circuit. Similarly, the gate of the second buffer pMOS transistor 204 is also connected to a connecting portion of a pair of transistors 202 and 203 which is the output portion of the first CMOS inverter circuit. The connecting portion of the transistors 205 and 206 is connected to the gate of the corresponding power transistor 102 as the output of the level conversion circuit 103.
It is desirable that an output voltage VHTM of the voltage generating circuit 117 does not exceed a breakdown withstand pressure of the CMOS inverter and the gate withstand pressure of the MOS transistor, but is set as much high as possible. If possible, the output voltage VHTM may be shared with the power source line VH for each heater 101. However, in an ordinary case, the driving voltage to each heater 101 is often set at a high value of 20V or more, while, on the other hand, the CMOS inverter is often fabricated by a semiconductor processing such as having its breakdown withstand voltage up to 15V. Further, since the gate withstand pressure of the MOS transistor depends on the thickness of a gate oxide film, the voltage applied to the gate of the MOS transistor is required to be a voltage sufficiently lower than the insulated withstand voltage of the gate oxide film. Therefore, it is difficult to match the optimum power source voltage (that is, the voltage VHTM) in the level conversion circuit 103 to the driving voltage (the voltage VH) of each heater 101. As a matter of fact, the additional provision of the power source line of the level conversion circuit 103 is conductive to a cost up of the whole system.
Hence, the conventional technology realizes the voltage generating circuit 117, for example, by a circuit structure as shown in FIG. 14. The circuit shown in FIG. 14 is constituted such that resistors R3 and R1 are connected in series between the power source line VH and a ground point, and an arbitrary voltage is prepared from the power line VH of the heater by a ratio of partial pressure of the resistors R3 and R1, to which a source follower circuit consisting of the nMOS transistor T1 as a buffer and a resistor R2 is connected, and the source of the nMOS transistor T1 is taken as an output end of the voltage generating circuit 117.
The circuit structure and the like as described above are disclosed in Japanese Patent Application Laid-Open No. H11-129479. As described above, the heater 101, the drive circuit and the like for driving the heater 101 are integrally provided, for example, on a silicon semiconductor substrate. Hence, the arrangement and the layout of each circuit portion on the silicon semiconductor substrate which constitutes the recording head will be described. FIG. 15 is a view to show one example of the layout of each circuit portion on the silicon semiconductor substrate. This is disclosed in Japanese Patent Application Laid-Open No. H08-108536.
In the silicon semiconductor substrate 150 having an approximate rectangular shape, there are arranged a plurality of heaters 101 so as to be alongside the one long side of the substrate, and each heater 101 is connected to the power transistor 102, respectively. In the drawing, the whole of the forming region of a plurality of power transistors 102 provided in such a manner is shown by a rectangular region 122. As illustrated, adjacent to the forming region (heater unit) of the heaters 101, the forming region 122 of the power transistors is arranged. Further, a drive logic circuit unit 123 in which a group of logic circuits including the level conversion circuits 103 and the shift resistor 116 shown in FIG. 13 are provided is provided adjacent to the forming region 122 of the power transistors at the side opposite to the forming region of the heaters 101. Though not illustrated, the drive logic circuit unit 123 is also connected to a wiring for supplying the transfer clock signal CLK, the image data DATA, the latch signal LT, and the heat signal HE.
The forming region 122 of the power transistors is connected to a power source line (power source wiring) 105 for applying a predetermined voltage to the heater 101, and the drive logic circuit unit 123 is connected to a GND (ground) line (GND wiring) 110 in which the current from the power transistor is let flow. Consequently, the power source line 105 corresponds to the power source line of the VH in FIG. 13, and the GND line 110 corresponds to the GNDH line. Though not illustrated, the drive logic circuit group 123 is also connected to the wiring for supplying the transfer clock signal CLK, the image data DATA, the latch signal LT, and the heat signal HE. Here, the power source line 105 is formed in such a manner as to be arranged on the element of each power transistor 102 by an aluminum wiring in a second layer in the semiconductor substrate 150 formed by a multi-layer wiring technology. On the other hand, a signal line and the like connected to the power transistor 102 are formed by the aluminum wiring in a first layer in the semiconductor substrate 150, and are electrically insulated from the power source line 105. In the present specification, the terminology of the aluminum wiring includes a wiring layer comprising an alloy including aluminum in addition to a wiring layer comprising a pure aluminum according to the common practice in the field of the manufacturing process of the semiconductor device. The terminology of the first layer and the second layer is used in such a manner as to define a layer close to the main body of the silicon semiconductor substrate as the first layer with the surface side defined as the second layer.
A wiring 106 is a wiring to connect the power source line 105 and the heater 101, and is directly connected by the aluminum wiring of the second layer in the semiconductor substrate 150. Further, a wiring 107 is a wiring to connect the heater 101 and the power transistor 102, and is formed by the aluminum wiring of the first layer of the semiconductor substrate 150. By providing the wirings 106 and 107 in this manner, the wiring 107 is passed through the underside of the power source line 105 which is the aluminum wiring of the second layer, and the power transistor 102 and the heater 101 can be directly connected. On the other hand, the GND line 110 is formed by the aluminum wiring of the second layer in the semiconductor substrate 150, and is arranged on each element constituting the drive logic circuit unit 123. On the other hand, the signal line and the like within the drive logic circuit unit 123 are formed by the aluminum wiring of the first layer, and is electrically insulated from the GND line 110. On the end portion of the power source line 105, there is provided a power source bonding pad 111, and on the end portion of the GND line 110, there is providing a GND bonding pad 112. In the example shown here, any of the power source line 105 and the GND line 110 is allowed to be pulled out to both of the left and right end sides of the semiconductor substrate 150, and at both of the left and right end sides, there are formed bonding pads 111 and 112.
However, in the above described recording head, when all the heaters 101 and power transistors 102 are connected to the VH wiring (power source line 105) and the GNDH wiring (GND line 110), with respect to the heaters arranged at the end of the heater unit and the heaters arranged at the center of the heat unit, a wiring resistance reaching those heaters is different. That is, depending on the position in the heater unit, the wiring resistance reaching that heater is different, and assuming that the driving voltage of the heater is constant, it is sometimes not possible to supply the same power to all the heaters. When a sum of the resistance between the VH wiring and the GND wiring, the wiring resistance, the heater resistance, and the ON resistance of the power transistor is different depending on the location of the heater, it is not possible to supply the same current value to all the heaters. Although a predetermined calorific value needs to be obtained even in the heater where the current to be supplied becomes the smallest, if the driving condition is set in such a manner, an excessive drive current is let flow in other heaters, and this ends up shortening the life of those heaters.
Further, the problem arising from the wiring resistance being not uniform noticeably emerges when the number of heaters arranged on the semiconductor substrate is increased with the recording head continuously lengthened or when the width of the power source line and the GND line are made small so as to shorten the length of the short side portion of the recording head.
Therefore, an object of the present invention is to provide a liquid ejection head semiconductor device, which is a semiconductor device for constituting the liquid ejection head represented by an ink jet recording head, wherein the irregularity of wiring resistance for each of a plurality of recording elements (for example, heaters) provided within this semiconductor device is made small, thereby preventing an excessive drive current from occurring in the recording elements.
Another object of the present invention is to provide a liquid ejection head and a liquid ejection apparatus using such a liquid ejection head semiconductor device.